1. Field of the Invention
The present invention relates to programmable logic devices, and more particularly, to an enhancement for existing industry standard programmable logic devices.
2. Description of the Related Art
The programmable logic device (PLD) industry has developed over the last several years to the point where a small number of PLD architectures dominate the industry, especially the industry for low density PLDs. As of the present date, these architectures, roughly described, are as follows:
16L8 A 20-pin device having 10 dedicated inputs, 2 dedicated combinatorial outputs, and 6 bi-directional I/O leads. The programmable array is made up of a programmable AND array followed by a fixed OR array, and each of the dedicated and bi-directional leads receives a respective output enable which is provided by the array. One ground lead and one power supply lead are provided.
16R8 A 20-pin device having 8 dedicated registered outputs, a clock input for clocking all the registers in common, and an output enable input for enabling the 8 outputs in common. The programmable array consists of a programmable AND array followed by a fixed OR array. One power and one ground lead are provided.
16R6 A 20-pin device having 8 dedicated inputs, 6 dedicated registered outputs, 2 bi-directional combinatorial outputs, a clock input for clocking all the registers in common, and an output enable input for enabling the 6 dedicated outputs in common. Two independent output enables are provided by the array for the two combinatorial outputs. The programmable array consists of a programmable AND array followed by a fixed OR array, and one power and one ground lead are provided. 16R4 A 20-pin device having 8 dedicated inputs, 4 dedicated registered outputs, 4 bi-directional combinatorial outputs, a clock input for clocking all the registers in common, and an output enable input for enabling the 4 dedicated outputs in common. Four independent output enables are provided by the array for the four combinatorial outputs. The programmable array consists of a programmable AND array followed by a fixed OR array, and one power and one ground pin are provided.
20L10 A 24-pin device having 12 dedicated inputs, 2 dedicated combinatorial outputs, and 8 bi-directional combinatorial I/O leads. The programmable array is made up of a programmable AND array followed by a fixed OR array, and each of the dedicated bi-directional leads receives a respective output enable which is provided by the array. One ground lead and one power supply lead are provided.
20L8 A 24-pin device having 14 dedicated inputs, 2 dedicated combinatorial outputs, and 6 bi-directional I/O leads. The programmable array is made up of a programmable AND array followed by a fixed OR array, and each of the dedicated and bi-directional leads receives a respective output enable which is provided by the array. One ground lead and one power supply lead are provided.
20R4 A 24-pin device having 12 dedicated inputs, 4 dedicated combinatorial bi-directional leads, 4 dedicated registered outputs, an output enable input and a clock input. The programmable array is made up of a programmable AND array followed by a fixed OR array. The output enable input controls the 4 registered outputs in common, and the clock input is provided to the 4 registers in common. Each of the bi-directional leads receives a respective output enable which is provided by the array. One ground lead and one power supply lead are provided.
20R6 A 24-pin device having 12 dedicated inputs, 6 dedicated registered outputs, 2 bi-directional combinatorial I/O leads, an output enable and a clock input. The programmable array consists of a programmable AND array followed by a fixed OR array. The output enable controls the 6 registered outputs, and the clock input is also provided to each of the 6 registers. Each of the bi-directional leads receives a respective output enable which is provided by the array.
20R8 A 24-pin device having 12 dedicated inputs, 8 registered outputs, a common output enable input provided to all the registered outputs and a common clock input provided to all the registers. The programmable array consists of a programmable AND array followed by a fixed OR array. One power and one ground pin are provided.
22V10 A 24-pin device having 11 dedicated inputs, 10 bi-directional outputs, and a shared data input/clock input. The array consists of a programmable AND array and a fixed OR array, and 10 of the array outputs are provided to the 10 respective bi-directional output leads via 10 respective output logic macrocells. Each macrocell can provide to its respective output a true or complement, registered or combinatorial, version of its input. A common asynchronous reset and a common synchronous preset are also provided to the macrocells from the array.
16V8 A 20-pin device having 8 dedicated inputs, 8 bi-directional outputs, an output enable input, and a clock input. The array consists of a programmable AND array and a substantially fixed OR array, and 8 of the array outputs are provided to the 8 respective bi-directional output leads via 8 respective output logic macrocells. Each macrocell can provide to its respective output a true or complement, registered or combinatorial, version of its input. The output enables are individually programmable to be high, low, responsive to the externally supplied output enable signal, or responsive to a respective AND array output.
20V10 A 24-pin device having 12 dedicated inputs, 8 bi-directional outputs, a thirteenth input which doubles as an output enable input, and fourteenth input which doubles as a clock input. The array consists of a programmable AND array and a substantially fixed OR array, and 8 of the array outputs are provided to the 8 respective bi-directional output leads via 8 respective output logic macrocells. Each macrocell can provide to its respective output a true or complement, registered or combinatorial, version of its input. The output enables are individually programmable to be high, low, responsive to the externally supplied output enable signal, or responsive to a respective AND array output.
All the above PLD architectures are described in various manufacturers' data books, for example, the "PAL Device Data Book" published by Advanced Micro Devices, copyright date 1990. The PAL Device Data Book is incorporated herein by reference.
These PLD architectures, and a few others, have each been widely accepted among PLD users. They are also available from a number of different manufacturers, all of which continue to use the above designators (e.g. "16L8", "22V10") to identify them as having the same internal architecture. The designators have also become widely recognized in the market as having particular, known architectural cores. There are numerous other varieties of PLD architectures available on the market, but they have not achieved the level of acceptance that has been achieved by the above devices. Thus they cannot be considered industry standard PLD architectures.
Industry standard PLD's generally have outputs which can supply a maximum of 16 to 24 milliamps in the low state and 3.2 milliamps in the high state. This output capability is adequate for driving 10 to 16 TTL loads, and therefore permits PLD's to be used in a wide variety of on-board logic-related applications. This drive capability is generally not enough for bus driving applications, however. For example, some of the most popular buses, such as the VME bus, require 48-64 milliamp drive capability. For bus driving applications, designers of board level products which incorporate PLD's have generally inserted dedicated bus interface elements between the PLD's and the bus. Such bus interface elements include bus interface registers, bus interface latches, bus buffers, bus interface transceivers and parity bus transceivers. Insertion of such elements between the PLD and the bus both increases the required board space and degrades performance.
Recently, some manufacturers have begun manufacturing PLD's with higher drive capability. Extra ground and power pins are generally required to support the extra drive capability, however, and these manufacturers have chosen to provide such extra pins by changing or cutting back the internal architecture of a device. For example, the PLX448, from PLX Technology Corp., is a 24-pin PLD with 9 dedicated inputs with hysteresis, one dedicated clock input, one combined clock/data input with hysteresis, and 8 bi-directional outputs with macrocells. The programmable array consists of a programmable AND array followed by a fixed OR array. Four of the bi-directional outputs can drive 24 milliamps in the low state, and the other four can drive up to 48 milliamps in the low state. As another example, the PLX464 has substantially the same architecture as the PLX448 except that it has four 48 milliamp drivers and four 64 milliamp drivers. The PLX448 and PLX464 and their data sheets are incorporated herein by reference.
Although the architectural core of the PLX448 and PLX464 can in some ways be considered to be somewhere between a 16V8 and a 22V10, the devices cannot be considered to be industry standard PLDs since they are not second sourced by any other manufacturer, and since their architectural core is not widely known in the market. Thus it is necessary for the manufacturer to explain to customers how the architecture differs from industry standard architectures such as the 16V8 and 22V10. That necessity can reduce the marketability of the devices.